1. Field of the Invention
The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same.
2. Description of the Background Art
Using silicon carbide instead of silicon is under active consideration in order to obtain power semiconductor devices with higher performance. So far, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having an ON resistance low enough to be theoretically expected from physical properties of silicon carbide has not been obtained. This is considered to be because channel mobility, which has a large influence on the ON resistance, has a value significantly smaller than a theoretical value expected from the physical properties of silicon carbide.
Unlike a MOSFET, a Junction Field Effect Transistor (JFET) can substantially avoid the problem of a reduction in channel mobility described above, because a large portion of a channel in the JFET is located inside a bulk crystal and is less influenced by a crystal surface. Thus, a JFET using silicon carbide is considered as a particularly promising power semiconductor device.
Yasunori Tanaka et.al, “700-V 1.0-mΩ·cm2 Buried Gate SiC-SIT (SiC-BGSIT)”, IEEE Electron Device Letters, Vol. 27, No. 11, (2006), pp. 908-910 proposes, as a silicon carbide semiconductor device, a device called a Static Induction Transistor (SIT) or a Junction Field Effect Transistor (JFET). The JFET has a buried gate composed of a p+ gate layer. A method for manufacturing the JFET includes the following steps. In the first step, an n− drift layer and a p+ gate layer are epitaxially grown on an n+ 4H—SiC substrate. In the second step, the p+ gate layer is subjected to dry etching to form a fine trench structure. In the third step, an n− channel region is formed by epitaxial growth to cover the trench structure.
In the above JFET, the width of a trench formed in the p+ gate layer corresponds to a channel width. Thus, in order to be able to control a channel without using an extremely high gate voltage, it is necessary to provide a trench having a fine width. If there are variations in the formation of the n− channel region which fills the trench, a pn junction surface formed of the p+ gate layer and the n− channel region has variations, and thus properties of the JFET vary. Accordingly, in the above method for manufacturing the JFET, it is necessary to perform fine processing for forming a fine trench and epitaxial growth for accurately filling the fine trench. Therefore, it is difficult to perform the above method for manufacturing the JFET.